1. Field of the Invention
The present invention generally relates to a semiconductor package, and more particularly to the stack package that one package consists at least two semiconductor chips stacked therein.
2. Description of the Related Art
Rapid progress in the memory chip has been presented to increase memory capacity. Currently, 128 M DRAM is mass-produced, and also the mass-production of 256 M DRAM will be available sooner or later.
For increasing memory chip capacity, i.e. high integration, a technology for inserting cells as many as possible into a given area of semiconductor device, is widely known. However, this method requires high technology such as a precise line width and a considerable amount of time for development. Accordingly, a relatively simpler stacking technology to optimize integrity of the semiconductor device has been developed most recently.
The term "stacking" used in semiconductor industry means a technique to double the memory capacity by heaping up at least two semiconductor chips in a vertical direction. According to the stacking technique, a 128 M DRAM device can be constituted by two 64 M DRAM devices for instance, also a 256 M DRAM device can be constituted by two 128 M DRAM devices.
Merely an example of a package fabricated according to the typical stacking technique is illustrated in FIGS. 1 and 2.
As shown in FIG. 1, a lead frame 2 is attached by means of an adhesive 3 to a semiconductor chip 1 in which a bonding pad is disposed on an upper portion of the semiconductor chip 1. An inner lead 21 of the lead frame 2 is connected to the bonding pad with a metal wire 3. The entire resultant is sealed with a molding compound 5 such that both ends of an outer lead 22 of the lead frame 2 is exposed therefrom.
On the package as constituted above, another package having the same constitution as above is stacked. That is to say, the outer lead 22 of the package in the upper position is in contact with a midway portion of the lead frame 2 in the lower position thereby electrically connecting each other.
However, there is a drawback in the general stack package that total thickness of the package is too thick. Further, since an electrical signal should pass the lead frame of the lower package through the outer lead of the upper package, there is another drawback that the electrical signal path is too long. Especially, bad connections are occurred frequently due to bad soldering since leads of both upper and lower packages are joined with each other by soldering.
A conventional stack package to solve foregoing problems is illustrated in FIG. 2.
As shown in the drawing, upper and lower semiconductor chips 1a,1b are opposed with a selected distance. An inner lead 21a of an upper lead frame 2a is attached on the bottom surface of the upper semiconductor chip 1a, thereby electrically connecting to a bonding pad of the upper semiconductor chip 1a with a metal wire 4a. Further, an inner lead 21b of a lower lead frame 2b is attached on the top surface of the lower semiconductor chip 1b thereby electrically connecting to a bonding pad of the lower semiconductor chip 1b with a metal wire 4b.
An outer lead 22a of the upper lead frame 1a is electrically bonded at a midway portion of the lower lead frame 2a by the laser and an outer lead 22a of the lower lead frame 2b is exposed from a molding compound 5a.
However, the stack package as illustrated in FIG. 2 incurs following shortcomings.
Although this type of stack package often shortens the electrical signal path, there may be occurred a signal interference during operation due to too short distance between the respective lead frames.
Furthermore, since the respective lead frames are opposed each other, there is a high probability of inferiority originated from the clearance between the lead frames. Since the respective lead frames are bonded by the laser, therefore an expensive laser equipment is required. Especially, as those lead frames are bonded semi-permanently, it is almost impossible to repair the device afterward. Further, when size of the chip is changed, it is required to manufacture new lead frames accordingly.
In addition to those shortcomings, an effective heat dissipation is not performed during operation since the respective semiconductor chips are positioned inside of the molding compound. That is, since there is no room for a heatsink for heat-dissipating function, the heat dissipation is performed inferiorly.